Nonvolatile flash memory devices store information in the form of charge in a flash memory cell. A flash memory cell may consist of a CMOS transistor with an additional floating metal gate between the substrate and the transistors gate or it may be constructed with no floating metal gate such that charge may be trapped in the insulator between the control gate and the channel. The charge is either stored in the floating gate or in the insulator and is injected to the floating gate during an operation known as programming. The charge may be removed during an operation known as an erase operation.
As the charge in the floating gate or insulator may vary contiguously, it is possible to store more than just one bit per flash transistor by using several charge levels to symbolize different sequences of bits.
FIG. 1 demonstrates a voltage level distribution for a 3 pbc (bits per cell) flash memory cell. The voltage level distribution includes eight lobes 101-108. Each lobe represents a 3-bit value.
The voltage level distributions of FIG. 1 illustrates non-overlapping lobes, however this is only schematic, and in practical cases the lobes may overlap. The reason for overlapping may be intentional for obtaining high programming speed, or due to the retention effect. For floating gate devices, an “old” page, may introduce greater overlap between lobes than a new page, since after many program/erase (P/E) cycles there is accumulated trap charge, which is de-trapped over time. After a long duration, every lobe may have a larger standard deviation (STD) and may have a different mean location. These effects are also known as retention.
The 3 bpc cell includes a most significant bit (MSB), a central significant bit (CSB) and a least significant bit (LSB). A physical page of flash memory module may store three logical pages. This physical page is programmed one logical page after the other. The programming includes various types of programming such as MSB programming (in which some of the cells are programmed to a single lobe and some are left in the erase state. At the end of this programming process only two lobes exists, the erase and the MSB lobes), a CSB programming (in which the erase lobe and the MSB lobe are each split into two lobes by further programming pulses, depending on the original state of each cell and the corresponding CSB bit. At the end of this step there are four lobes) and a LSB programming (in which each of the four lobes is further split to create 8 lobes, overall). The logical pages are read by applying various types of read operations such as MSB read (in which a MSB threshold 114 is used), CSB read (in which two CSB thresholds 112 and 116 are used) and LSB read (in which four LSB thresholds 111, 113, 115 and 117 are used). FIG. 2 shows similar distributions for the case of 2 bpc devices.
The previous paragraph describes one method. There are several methods for programming 8 lobes.
A NAND flash array (or block) is constructed from NAND flash memory cells. The NAND flash memory cells are grouped into columns (or strings). FIG. 3 shows a typical prior art portion 30 of a NAND flash memory array that includes thirty two lines (wordlines 31(1)-32(32)) and multiple (Q) columns (32(1)-32(Q).
Once Colum 32(q) is illustrated in further details—it shows the thirty two flash memory cells 34(q) of the column, bit line select transistor and ground select transistor, and the voltages 33(q) supplied to the transistors and flash memory cells (Bit Line Select, Vbias, Vth). Column 32(q) is connected to sense amplifier 35(q), that in turn is connected to latch 36(q). A string (column) is duplicated many times (for example Q=34560-250000 times) in a block and includes several (for example—thirty two) flash memory cells. Each of the flash memory cells is associated with a different wordline (or row) which connects all of the corresponding cells in the other strings of the block. When a block is chosen, each string is connected to a corresponding bitline by turning on the Bit Line Select and the Ground Select transistors. When a read operation is performed, a sense amplifier is connected to the bit-line and after allowing some time (say 25-125 uS) for the bit-line voltage to settle, the result is stored by a latch.
In order to measure the charge in a certain cell within a string, all other cells are switched on by applying a high voltage on their gates (given by Vbias) and a comparison voltage, Vth, is applied to the gate of the selected cell. If the cell is charged and Vth is not high enough, the gate will not allow current to flow and the sense-amplifier will output a “0”. On the other hand, if the cell is not charge or Vth is high enough, current will flow and the sense-amplifier will output a “1”. Different schemes may exist where the cell being samples is biased with a constant voltage (say Vcc) but in the sense-amplifier a comparison against a reference string is performed which reference value may be determined by some external voltage, Vth.
The above sampling technique holds when a bit may be obtained only through a single threshold comparison. When more than a single threshold comparison is required, the above procedure may be performed for each threshold and the results may then be combined. Alternatively, several sense-amplifiers may be used simultaneously, each one compares against a different threshold, and the results are then combined to yield the required bit value.
All cells in a word-line (physical page) are programmed simultaneously and read simultaneously. In case of MLC or TLC, the programming of a wordline is divided into two or three stages, referred to as MSB, CSB and LSB page programming stages.
Above we described a standard floating gate planar NAND device. Historically, planar NAND design enabled continued storage capacity density improvements through continuous shrinking of the basic cell feature sizes from one NAND technology node to the next, reducing the basic gate size from 48 nm-41 nm-32 nm-25 nm-19 nm. However, it is proving harder and harder to shrink the basic silicon process feature size for several reasons. The main reasons include: a. limitations in the tools required and b. limitation in the reliability of a single NAND flash cell. The NAND Flash cell reliability is primarily determined by the number of electrons use to store a state in a cell. In smaller technology nodes (such as 16 nm) the number of electrons per state in a cell becomes very small (a few tens), greatly reducing the reliability of the stored information.
Therefore, it has been suggested to produce a multi-layered NAND Flash memory array which overcome the limits of planar NAND design and which continues with current trends in storage density improvements. It was suggested that in a multi-layered NAND Flash array, the basic feature size will be much larger than current planar NAND feature size (e.g. 40 nm instead of 19 nm) and thus eliminating the problems associated with such small technology nodes (namely, tooling and NAND transistor reliability). However, to allow improvement in density, the NAND arrays are to be stacked one on top of the other, 64-128 floor high. Thus, obtain a gain in the vertical dimension, which is higher than the loss due to going back from a 19 nm to 40 nm technology node. The introduction of NAND cell in a third dimension earned this technological advancement the name of 3D NAND.
There are various manners to build 3D NAND device and still allow the reduction in cost per bits, even though the production process has become more complicated and requires more steps. One of the key steps which allows the reduction of the cost is etching or hole drilling which enables to simultaneously produce multiple NAND gates on several floors, without increasing the cost linearly with the number of floors.
Several methods have been suggested for producing 3D NAND which differ in how the NAND cells are organized in space. Non-limiting examples of 3D NAND arrays include the bit cost scalable (BiCS) standard memory, pipe shaped BiCS memory (p-BiCS) of Toshiba, the terabit cell array transistor (TACT) of Toshiba, the Vertical recess array transistor (VRAT) of Samsung, a 3D dual control-gate with a surrounding floating-gate of Hynix.
In a vertical channel design, the NAND Flash bit-line or column described previously and in FIG. 3, end up as a vertical column, perpendicular to the base axis of the die. This is also shown schematically in FIG. 5 where multiple vertical planes 101(1)-101(J), each having an array of flash memory cells 101(1)-102(J) connected via bit lines 103. In general the j'th plane (j ranging between 1 and J) 101(j) has multiple pages (such as page 4) each page (or row) includes multiple flash memory cells and the cells of each page are read concurrently.
All pages belonging to the same bit-lines (to the same plane) constitute a block—thus planes 101(1)-101(J) form J erase blocks. As in the planar case, all cells belonging to the same block are erased simultaneously and all cells belonging to the same page/row are programmed simultaneously. A block may constitute more than one plane, as shown in FIG. 6 in which erase block 105(1) includes two planes 101(1) and 101(2).
FIG. 7 shows a slightly more complex structure of vertical channel 3D NAND. This is Toshiba's p-BiCS structure where each bit-line is actually made of two vertical lines connected at the bottom (U-shape) and flash memory cells are arranged in pairs such as pairs 106(1)-106(4)—wherein one flash memory cell of the pair is connected to one vertical line and the other flash memory cell of the pair is connected to the other vertical line (both vertical lines are connected at their bottom).
In a vertical channel 3D NAND the NAND Flash bit-line or column is horizontal to the base axis of the die, as shown in FIG. 4. The bit-line and rows are defines in a similar manner as in the vertical channel. The planes 101(1)-101(J) are horizontal.
A 3D NAND array adds additional disturb factors. One of these is additional cell to cell coupling. Now each cell has many more neighboring cells. Instead of nine neighboring cells in a planar NAND (four near neighbors and four diagonal), now there are twenty six neighbors to each cell 200 (see FIG. 9) where we can distinguish between three levels of neighbors. Six level one neighbors 201, twelve level two neighbors 202 and eight level three neighbors 203. Thus, the charge stored on neighboring cells may affect the threshold voltage of the center cell.
Cell to cell coupling in 3D NAND is also different than in planar NAND through coupling between different blocks. Different blocks may affect one another through the cells on their borders. Since in standard NAND, block programming order is arbitrary, it is difficult to control the coupling effects on the boarders of the blocks.
It should be noted that cell to cell coupling may vary, depending on 3D NAND implementation and may also exhibit no coupling due to the basic structure of the NAND cell. However, it is inevitable that as 3D NAND device technology node will shrink to increase density, so will cell to cell coupling will become more severe.
The coupling effect between cells is further increased when multiple bits per cell are programmed due to the larger charge and larger voltages.
In the following we present methods to limit the amount of disturb from neighboring cells using methods of programming ordering, depending on the 3D NAND structure, read back coupling cancellation methods and block management schemes.